The term “transceiver” is used herein to denote any device that performs the functions of a transmitter and a receiver. The term “transmitter” is used herein in a broad sense to denote any device capable of transmitting data over a link (e.g., a serial link), and optionally also capable of performing additional functions which can include encoding and/or encrypting the data to be transmitted. The term “receiver” is used herein in a broad sense to denote any device capable of receiving data that has been transmitted over a link (e.g., a serial link), and optionally also capable of performing additional functions which can include decoding and/or decryption of the received data, and other operations related to decoding, reception, or decryption of the received data.
A transceiver typically includes a data sampling circuit that includes a feedback loop for controlling the phase of a sampling clock. Such a feedback loop typically includes a phase detector (“PD”) that determines the phase error (O) present between a sampling clock and data being sampled by the sampling clock. Typically, the phase detector determines the phase error between the sampling clock and a reference clock derived from the data being sampled by the sampling clock.
The expressions “high frequency operation” and “high speed operation” are used herein synonymously to denote operation of a circuit in response to an input signal (e.g., an input clock) having frequency of 1 GHz or more (e.g., an input clock having frequency 5 GHz or 5.15625 GHz).
Transceivers (sometimes referred to as “10 Gb Ethernet transceivers”) that comply with the recently established standard known as the “10 Gb Ethernet” standard (IEEE 802.3-ae, promulgated in 2002, entitled CSMA/CD Access Method and Physical Layer Specifications-MAC Parameters, Physical Layer and Management Parameters for 10 Gb/s Operation”) have been implemented.
Scaled-down technology and low supply voltage allow a 10 Gb Ethernet transceiver to be implemented in a single CMOS integrated circuit which includes a 10.3125-Gb/s serial interface and a four-channel 3.125-Gb/s interface (XAUI). See, for example, the transceiver described in Sidiropoulos, et al., “An 800 mW 10 Gb Ethernet Transceiver in 0.13 μm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 168–169, February 2004.
For physical coding sub-layer (PCS) and management functions, it is conventional for a 10 Gb Ethernet transceiver to employ an elastic buffer or gearbox that uses 312.5 MHz and 322.27 MHz read/write clocks to generate 10.3125-Gb/s serial data in response to quad 3.125-Gb/s data, to generate quad 3.125-Gb/s data in response to 10.3125-Gb/s serial data, and to handle 64/66b coding. A 10 Gb Ethernet transceiver typically also includes a clock-multiplying unit (“CMU”) or clock-and-data recovery unit (“CDR”) that generates a 5.15625 GHz clock. A 10 Gb transceiver typically also includes a divide-by-16 frequency divider circuit (“÷16” circuit) and a divide-by-16.5 frequency divider circuit (“÷16.5” circuit) that generate, respectively, a 322.27 MHz clock and a 312.5 MHz clock in response to the 5.15625 GHz clock output from the transceiver's CMU or CDR. The 322.27 MHz and 312.5 MHz clocks can be supplied to divide-by-2 frequency divider circuits (to generate 161.135 MHz and 156.25 MHz clocks), and the 161.135 MHz and 156.25 MHz clocks can be used in feedback loops of data sampling circuits for sampling the 10.3125-Gb/s and 3.125-Gb/s data. Alternatively, the 322.27 MHz and 312.5 MHz clocks themselves can be used in feedback loops of data sampling circuits for sampling the 10.3125-Gb/s and 3.125-Gb/s data.
A 10 Gb Ethernet transceiver can be implemented as an integrated circuit, for example, using a 0.13-μm CMOS technology. Such an advanced CMOS technology offers fast transistor speed to achieve 10 Gb/s operation, but also poses design challenges. For example, in a PLL for generating a clock (e.g., a sampling clock) for such an integrated circuit implementation of a 10 Gb Ethernet transceiver, the reduced supply voltage narrows the input voltage range of the VCO of the PLL. If the PLL has conventional design, the reduction in supply voltage implies that VCO gain must be increased in order for the PLL to be operable over the desired frequency range under all possible PVT conditions (i.e., all possible variations in process, voltage, and temperature parameters during manufacture and operation). For example, a VCO implemented as an integrated circuit using a 0.13-μm CMOS technology and operating with a 1.2 Volt supply voltage may require a voltage-to-frequency gain of as high as 10 GHz/V to cover the desired frequency range under all possible PVT conditions.
Voltage-to-frequency gain of a VCO (sometimes denoted herein as “Kvco”) is the slope of the curve indicating the VCO's output clock frequency as a function of control voltage. The functional relation of output clock frequency versus control voltage for a VCO, will sometimes be referred to herein as the “frequency-voltage characteristic” of the VCO.
Operation of a VCO having high Kvco in a PLL undesirably causes the PLL to have high noise sensitivity, since noise on the power supply and control node is modulated onto the VCO output. To make a PLL (including a VCO) operable under a wide range of PVT conditions without the need for high Kvco, it has been proposed to design the VCO to be operable with any selected one of multiple frequency-voltage characteristics each having low Kvco, with sufficient frequency overlap between the characteristics, rather than to be operable in accordance with only one frequency-voltage characteristic having large Kvco in a desired operating range. In operation of a PLL including such a VCO (sometimes referred to as a “multi-range VCO”), coarse control is achieved by causing the VCO to operate with a selected “best” one of the available frequency-voltage characteristics, and fine control is achieved by causing the VCO to operate at a “best” operating point along the selected frequency-voltage characteristic. Generally, to avoid malfunction or false operation of a PLL that includes a multi-range VCO, the PLL should satisfy the following conditions: each operating frequency must be included within a segment of at least one of the frequency-voltage characteristics; there must be sufficient frequency overlap between the frequency-voltage characteristics so that the PLL can operate at any target frequency in the full range of operating frequencies (the range of frequencies at which the PLL is intended to be operable) and the PLL can be switched between different ones of the frequency-voltage characteristics to operate at any frequency in the full range; the PLL can be switched to the appropriate frequency-voltage characteristic sufficiently rapidly regardless of initial conditions (i.e., the conditions at power on or reset); and the PLL must operate with adequate immunity to noise.
FIG. 1A is a graph of a frequency-voltage characteristic of a VCO which operates in a PLL only in accordance with this characteristic. To allow the PLL to operate at any frequency in the full range from f1 to f2 in response to control voltages V in the range VL<V<VH, where VL is a minimum control voltage and VH is a maximum control voltage, the characteristic has relatively large slope (Kvco) throughout that operating range. FIG. 1B is a graph of a set of frequency-voltage characteristics of a VCO. A modified version of the PLL of FIG. 1A includes the VCO of FIG. 1B. This modified PLL includes a coarse control loop which implements a coarse control algorithm to ensure that the VCO of FIG. 1B always operates in accordance with a current best (selected) one of the frequency-voltage characteristics. Each characteristic graphed in FIG. 1B has a relatively small slope (VCO gain). By operating in accordance with a sequence of different ones of these characteristics, the VCO of FIG. 1B can operate at any frequency in the same range (from f1 to f2) as does the VCO of FIG. 1A in response to control voltages in the same range (from VL to VH) as does the VCO of FIG. 1A. There is sufficient frequency overlap between the frequency-voltage characteristics of FIG. 1B to allow the coarse control loop to switch between them. Fine control of the PLL of FIG. 1B is achieved by choosing the best operating point along the currently selected one of the frequency-voltage characteristics.
In PLLs that use VCOs having inductor and capacitor-based design (“LC” VCOs), it is conventional to implement coarse control (of the type mentioned in the two previous paragraphs) with a coarse control loop and to implement fine control (of the type also mentioned in the two previous paragraphs) with a fine control loop (see, for example, T. H. Lin et al., “A 900 MHz 2.5 mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” J. Solid-State Circuits, vol. 36, pp. 424–431, March 2001).
Two schemes have been employed to implement such a coarse control loop: monitoring the VCO's control voltage (for example, as described in the above-referenced paper by Lin, et al.); and directly counting edges of the VCO's output clock signal to determine its frequency directly. FIG. 2 shows circuitry for use in a conventional coarse control loop to monitor a VCO's control voltage. Since a typical LC VCO includes a MOS varactor having predictable tuning range, the FIG. 2 circuitry can be used to monitor the control voltage and achieve coarse control of an LC VCO (e.g., select a best one of multiple available frequency-voltage characteristics for the LC VCO). The FIG. 2 circuitry allows coarse control to be achieved by inferring the frequency of the VCO's output clock from the control voltage measurements using assumptions about the currently employed frequency-voltage characteristic. In operation of a coarse control loop that includes the FIG. 2 circuitry, the voltage comparators shown in FIG. 2 compare predetermined voltages VH and VL with a low-pass-filtered version (identified as “Vcap” in FIG. 2) of the fine control voltage currently being applied to the VCO. The output of the comparators is sampled, and the samples are asserted to an Up/Down counter. The Up/Down counter generates control signals for controlling the switch positions of a switched-capacitor (SC) network (not shown in FIG. 2) in response to the sampled outputs of the comparators, to allow the coarse control loop to select an assumed “best” one of multiple available frequency-voltage characteristics for the VCO. As long as predetermined voltage conditions are met (i.e., when the voltage Vcap satisfies VL<Vcap and Vcap<VH), the coarse control loop does not change the frequency-voltage characteristic of the VCO, but a fine control loop operates continuously to control the operating point along the current frequency-voltage characteristic. Coarse control implemented using the FIG. 2 circuitry is adequate where the VCO's voltage-frequency relationship is predictable and does not change unless it is changed by the coarse control loop. However, if the VCO's frequency-voltage characteristic changes (e.g., as a result of a temperature change or other environmental change) without being affirmatively changed by the coarse control loop, or if the coarse control loop otherwise makes a wrong assumption about the current frequency-voltage characteristic for the VCO, the coarse control loop will infer an incorrect current VCO output frequency from the control voltage measurements and its (incorrect) assumptions about the currently employed frequency-voltage characteristic, and thus will not generate appropriate control signals for controlling the switch positions of the switched-capacitor (SC) network to select a “best” one of the multiple available frequency-voltage characteristics for the VCO.
For example, when the voltage Vcap satisfies VL<Vcap and Vcap<VH but is much closer to VH than to VL, the FIG. 2 circuitry would not change the VCO's frequency-voltage characteristic, even where there is a high probability that a small change in supply voltage or temperature will cause the control voltage to rise above VH without any significant change in VCO output frequency (and although neither the coarse control circuitry nor fine control circuitry causes any change in operation of the VCO). If, for example, a small temperature change shifts the frequency-voltage characteristic downward, thereby increasing the control voltage to a value above VH (without significantly changing the VCO output frequency), the FIG. 2 circuitry could undesirably cause a compensating change in the frequency-voltage characteristic that raises the control voltage, which then causes the fine control circuitry to decrease the control voltage to a level just slightly above VL. In this state, another slight change in supply voltage or temperature (lowering the control voltage to below VL without changing the VCO frequency) could cause the FIG. 2 circuitry to execute another compensating change in the frequency-voltage characteristic, resulting in another move of the control voltage to another unstable value (a value slightly below VH), and so on. To prevent such unstable operation, in which the coarse control circuitry changes frequency-voltage characteristics too frequently, hysteresis must be provided. However, provision of hysteresis (e.g., by employing additional voltage comparators with reference voltages higher than VH and lower than VL) would have disadvantages (e.g., it could reduce the operating range of a selected frequency-voltage characteristic).
Another conventional scheme for implementing coarse control of a VCO (other than by VCO control voltage monitoring as described with reference to FIG. 2) is a frequency counting scheme in which edges of the VCO's output clock signal (and edges of a reference clock whose frequency is the target frequency) are counted directly. By counting such clock edges, a coarse control loop can compare the VCO output clock and reference clock frequencies and determine whether the output clock frequency is greater or less than the target frequency. Since this scheme does not assume any particular voltage-frequency relationship for the VCO, it can be used with a VCO whose operating range is less predictable than that of a typical LC VCO. However, the frequency counting method cannot itself resolve the ambiguity as to which one of multiple available frequency-voltage characteristics (all containing the target frequency) should be selected. One technique for resolving such ambiguity is to implement the PLL's coarse control loop to use predetermined rules to choose one of the candidate frequency-voltage characteristics. For example, the rules can select the lowest (or highest) candidate frequency-voltage characteristic (e.g., the candidate characteristic having lowest or highest average frequency in a given control voltage range). However, since the frequency counting method does not measure the actual control voltage, a coarse control loop relying only on the frequency counting method cannot reliably select (as an optimal frequency-voltage characteristic) one of multiple available frequency-voltage characteristics which has the target frequency nearest to the middle of its control voltage range. To reliably select (as an optimal frequency-voltage characteristic) the one of multiple candidate frequency-voltage characteristics which has the target frequency nearest to the middle of a control voltage range, a coarse control loop relying on the frequency counting method must also implement some other control technique (e.g., a complicated technique including a sweep through each of the candidate characteristics and selection of one of the candidate characteristics in which the target frequency lies nearest to the middle of the control voltage range).
It had not been known until the present invention how to implement both coarse and fine control loops in a PLL for reliable (but simply implemented) control of a ring oscillator (“ring OSC”) or other VCO whose voltage-frequency characteristic is unpredictable or changes even when not affirmatively changed by the coarse control loop. The frequency-voltage characteristic of a PLL using a ring OSC as a multi-range VCO is less predictable than that of a PLL using an LC VCO in place of the ring OSC, and tends to change during operation of the PLL even when not affirmatively changed by the coarse control loop. Preferred embodiments of the present invention implement coarse control of a PLL (whose multi-range VCO is implemented as a ring OSC), e.g., a PLL in a clock and data recovery (CDR) circuit, in accordance with a robust algorithm to avoid the need for frequent resetting of the PLL's coarse control loop.